The present invention pertains to random access memory apparatus and methods, and more particularly, to a method and apparatus for decreasing the average access time of a random access memory system.
Random access memories are one of the most important functional components of a data processing system and frequently they dictate or limit the operational speed of the system. In addition, they frequently are a significant portion of the hardware of a data processing system, and thus account for a significant portion of the system's cost. Since storage capacity of random access memories is directly related to the overall cost of a data processing system, the size of such memory is an important factor when considering the design of the overall processing system; further, since random access memory speeds have become the limiting factor in some systems, an increase in the information access speed (decrease in access time) of the memory represents an increase in overall system power. For example, instruction storage units must be capable of sufficiently rapid access time to provide instructions to the data processing unit for it to operate upon data without the necessity of waiting for the delivery of such instructions.
The prior art has attempted to increase the speed of instruction storage units by various means. For example, U.S. Pat. No. 3,764,988--Onishi, describes an instruction processing device that differentiates between types of instructions to expedite retrieval of information in memory in preparation for execution of the next instruction. In this patent, the increased instruction unit speed is achieved through detection of branch instructions that result in advanced fetching of information in preparation for subsequent instructions. The fetching of the data is nevertheless constrained by the type of memory used in a manner described above. In U.S. Pat. No. 3,775,756--Balser, the next instruction to be supplied to the processor is retrieved from the instruction memory and stored in an instruction register. The accessing and retrieval of the individual instructions from the instruction memory is, however, conventional and the speed limitations of the storage unit containing the instructions will limit the operational speed of the overall system unless high speed storage devices are used.
Random access memories have been constructed utilizing bipolar or high speed emitter coupled logic (ECL) chips. However, such ECL chips are relatively expensive when compared with the slower, high storage capacity, metal oxide semiconductor (MOS) chips. Thus, the relatively slow access time required of instruction storage units using MOS chips (usually around 400 nanoseconds), is a major limitation of their use. Conversely, ECL technology presently operates at a much higher speed (around 25 nanoseconds) but a major limitation of its use is its small storage capacity per chip (or high cost per bit of storage).
It is therefore an object of the present invention to provide a method and apparatus for decreasing the access time of a random access memory while retaining the benefits of high storage capacity but slower circuit construction techniques.
It is another object of the present invention to provide a method and apparatus for decreasing memory access time in an instruction storage unit while using relatively low speed random access memory circuit chips.
It is still another object of the present invention to provide a method and apparatus for increasing the speed of a random access memory by permitting groups of words or instructions to be accessed at a relatively low speed while selectively utilizing high speed elements within the memory array to select specific words or instructions from the previously accessed group.
These and other advantages of the present invention will become apparent to those skilled in the art as the description thereof proceeds.